Switching Performance Investigation of a Gate-All-Around Core-Source InGaAs/InP TFET
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Transactions on Electrical and Electronic Materials https://doi.org/10.1007/s42341-020-00257-1
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Switching Performance Investigation of a Gate‑All‑Around Core‑Source InGaAs/InP TFET Danial Keighobadi1 · Saeed Mohammadi1 · Mohaddeseh Mohtaram1 Received: 30 May 2020 / Revised: 26 September 2020 / Accepted: 31 October 2020 © The Korean Institute of Electrical and Electronic Material Engineers 2020
Abstract A novel core-source gate-all-around TFET based on InGaAs/InP heterojunction is presented in this paper. In the proposed device, the main current flow mechanism is line tunneling which occurs across a heterojunction composed of a narrowbandgap material of source and a wide-bandgap material of channel. The off-state current and ambipolar conduction are diminished by simultaneously employing two different doping concentrations in the channel region, as well as a wide-bandgap material in drain region. We study the switching performance of the device using a calibrated numerical device simulator. The results indicate impressive performance of the proposed transistor, including an extremely steep subthreshold swing, sub 3mv/dec over 5 decades and sub 60mv/dec over 9 decades of drain current, and average subthreshold swing of about 27mv/ dec, and an on-state to off-state current ratio of about 1 011 at VGS = 0.3 V. The impact of variations in the device dimensions, doping and bias condition on its electrical characteristics is also studied and discussed physically. Keywords Tunnel FET · Core-source · InGaAs/InP · Line tunneling · Switching performance
1 Introduction One of the most challenging issues in nanoelectronics is power consumption. Over the decades, MOSFETs have been unrivalled building block of overwhelming majority of VLSI circuits; however, necessities of nanoelectronics industry have obliged device researchers to invent new transistors. Although novel MOSFET architectures, such as FinFETs [1], could resolve some of the scaling problems of the conventional devices, but their performance is still limited to the fundamental switching limit of MOSFETs. The idea of inventing TFET has originated from Esaki tunnel diode, and from the outset, it was clear that it is a remarkable achievement in nanoelectronics. Sub 60mv/dec subthreshold swing (SS), very low off-state current (Ioff), small required supply voltage, along with compatibility with CMOS technology are the promising features of TFETs, although low onstate current (Ion) and ambipolar conduction are the main drawbacks.
* Saeed Mohammadi [email protected] 1
Electrical and Computer Engineering Department, Semnan University, Semnan, Iran
In order to resolve the shortcomings and improve the benefits of TFETs, researchers have addressed the issue utilizing different materials and/or geometrical architectures in their proposed devices. TFETs based on Si-Ge [2–6] and III-V [7–10] heterostructures, carbon materials [11, 12], two dimensional materials [13], L-shaped, U-shaped, and Z-shaped gate [14–18], core–shell, nanowire and nanotube
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