Fabrication of Air-Gaps Between Cu Interconnects for Low Intralevel k.
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Fabrication of Air-Gaps Between Cu Interconnects for Low Intralevel k. Dhananjay M. Bhusari, Michael D. Wedlake, Paul A. Kohl, Carlye Case1, Fred P. Klemens1, John Miner1, Byung-Chan Lee2, Ronald J. Gutmann2, J.J.Lee3, Robert Shick4 and L. Rhodes4 School of Chemical Engineering, Georgia Institute of Technology, Atlanta, GA. 1 Lucent Technologies, Murray Hill, NJ. 2 Rensselaer Polytechnic Institute, Troy, NY. 3 Motorola Inc., Austin, TX. 4 BF Goodrich Company, Brecksville, OH. ABSTRACT We present here a method for fabrication of air-gaps between Cu-interconnects to achieve low intralevel dielectric constant, using a sacrificial polymer as a ‘place holder’. IC compatible metallization and CMP processes were used in a single damascene process. The air-gap occupies the entire intralevel volume between the copper lines with fully densified SiO2 as the planer interlevel dielectric. The width of the air-gaps was 286 nm and the width of the copper lines was 650 nm. The effective intralevel dielectric constant was calculated to be 2.19. The thickness of the interlevel SiO2 and copper lines were 1100 nm and 700 nm, respectively. Further reduction in the value of intralevel dielectric constant is possible by optimization of the geometry of the metal/air-gap structure, and by use of a low k interlevel dielectric material. In this method of forming air-gaps, the layer of sacrificial polymer was spin-coated onto the substrate and formed into the desired pattern using an oxide or metal mask and reactive-ionetching. The intralevel Cu trench is then inlaid using a damascene process. After the CMP of copper, interlevel SiO2 is deposited by plasma-CVD. Finally, the polymer place-holder is thermally decomposed with the decomposition products permeating through the interlevel dielectric material. The major advantages of this method over other reported methods of formation of air-gaps are excellent control over the geometry of the air-gaps; no protrusion of air-gaps into the interlevel dielectric; no deposition of SiO2 over the side-walls, and no degradation of the interlevel dielectric during the formation of air-gap. INTRODUCTION The need for developing new low dielectric constant (low-k) materials as intralevel dielectrics in the integrated circuits (ICs) arises from the continuing shrinkage in the size of the features in the ICs. The increased proximity of the metallic interconnects introduces propagation delays, crosstalk noise, and increases power dissipation as a result of higher resistancecapacitance coupling[1]. The National Technology Roadmap for Semiconductor, therefore, calls for qualification/preproduction of materials with k = 2.5 - 2.0 in 2000; and k = 1.5 – 2.0 in 2003[2]. As a consequence, several inorganic as well as polymeric materials are being developed to achieve low k [3-5]. However, since these materials are required to satisfy several stringent requirements such as low moisture absorption, excellent adhesion to a variety of materials, high Tg, thermal stability, good mechanical properties and also be able to be in
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