Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog an
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ORIGINAL PAPER
Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance Arighna Basak 1 & Angsuman Sarkar 2 Received: 31 July 2020 / Accepted: 14 October 2020 # Springer Nature B.V. 2020
Abstract This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/ RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications. Keywords Drain current modeling . Asymmetric . Dual material double gate . Cut-off frequency . Transconductance generation factor . Gain bandwidth product
1 Introduction Continuous downscaling of semiconductor devices was strongly prejudiced by the modern developments in device fabrication technology and channel engineering for realizing enhanced performance. As the destructive downscaling of MOSFET dimension, the gate decreases its control over the region of channel, which is due to increase numerous Short Channel Effects (SCEs) [1–3]. To overcome this situation, the semiconductor engineers examine and explore novel device
* Arighna Basak [email protected] Angsuman Sarkar [email protected] 1
Department of ECE, Brainware University, Kolkata, West Bengal, India
2
Department of ECE, Kalyani Government Engineering College, Kalyani, India
structures for additional improvements of the device performance in terms of reduced SCEs [4–6]. In this context, having vigorous discretization junctionless MOSFET structures [7–11] evolved as a promising candidate for diminishing SCEs and improved scalability. Owing to this junctionless behaviour, it improves the challenges of large concentration of doping and economical thermal budget. Moreover, Dual Material Double Gate MOSFET (DMDG MOSFET) structure [12, 13] with two materials in gate region employs through dissimilar work functions positioned side by side for improving SCEs. In addition, asymmetric operation provides a supplementary degree of freedom to optimize OF
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